#!/bin/bash

echo "#Generating the .sdc and .spef files needed for timing analysis"
echo "#Author: Min Li, Contact: mli46@wisc.edu"
echo -ne "#Generated Date: "
date
echo 

export VERILOG_FILE=$HSTA_BENCHMARK_DIR\/$HSTA_BENCHMARK".v"
export SDC_FILE=$HSTA_BENCHMARK_DIR\/$HSTA_BENCHMARK".sdc"
export SPEF_FILE=$HSTA_BENCHMARK_DIR\/$HSTA_BENCHMARK".spef"

echo "SDC file is "$SDC_FILE
echo "SPEF file is "$SPEF_FILE

awk '/input/ {print} ' $VERILOG_FILE | awk -vRS=";" -vFS=" " '{print $2}' > temp1.txt
awk '/output/ {print} ' $VERILOG_FILE | awk -vRS=";" -vFS=" " '{print $2}' > temp2.txt

## Remove empty lines. don't know why they come 
sed -i '/^$/d' temp1.txt
sed -i '/^$/d' temp2.txt


rm -rf $SDC_FILE
## Generating the .sdc file
echo "# Generating the .sdc file"
echo "# clock definition" >> $SDC_FILE
## cycle value need to be tested to get the optimal 
echo "create_clock -name clk -period $HSTA_CYCLE_PERIOD [get_ports blif_clk_net]" >> $SDC_FILE
#echo "set_dont_touch_network [get_ports blif_clk_net]" >> $SDC_FILE
#echo "set_dont_touch_network [get_ports blif_reset_net]" >> $SDC_FILE
echo "set_false_path -from [get_ports blif_reset_net]" >> $SDC_FILE
echo >> $SDC_FILE

echo "# input delays" >> $SDC_FILE
awk '!/blif_clk_net/ {printf("set_input_delay 0.0 [get_ports %s] -clock clk\n"),$1} ' temp1.txt >> $SDC_FILE
echo >> $SDC_FILE

## make sure the driver gate type and transition values are what specified in the library
echo "# input drivers" >> $SDC_FILE
awk ' {printf("set_driving_cell -lib_cell AO33D0BWP -library tcbn45gsbwpbc [get_ports %s] -input_transition_fall 0.01 -input_transition_rise 0.01\n"),$1} ' temp1.txt >> $SDC_FILE
#awk ' {printf("set_driving_cell -lib_cell AO33D0BWP -library tcbn45gsbwpbc [all_inputs] -input_transition_fall 0.01 -input_transition_rise 0.01\n"),$1} ' temp1.txt >> $SDC_FILE
#echo "set_driving_cell -lib_cell AO33D0BWP -library tcbn45gsbwpbc [all_inputs] -input_transition_fall 0.01 -input_transition_rise 0.01" >> $SDC_FILE
echo >> $SDC_FILE

# set input transition
# echo "# input transitionss" >> $SDC_FILE
# awk ' {printf("set_input_transition [get_ports %s] -fall 0.01 -rise 0.01  -clock clk \n"),$1}' temp1.txt >> $SDC_FILE
# echo >> $SDC_FILE

echo "# output delays" >> $SDC_FILE
awk ' {printf("set_output_delay 0.0 [get_ports %s] -clock clk\n"),$1} ' temp2.txt >> $SDC_FILE
echo >> $SDC_FILE

## Make sure the output load value
echo "# output loads" >> $SDC_FILE
awk ' {printf("set_load -pin_load 1.0 [get_ports %s]\n"),$1} ' temp2.txt >> $SDC_FILE
echo >> $SDC_FILE
echo "done"

#echo "No .spef generation, exit"
#exit

rm -rf $SPEF_FILE
## Generating the .spef file
echo "# Generating the .spef file"

awk 'BEGIN {flag=0;} { \
if (flag == 1){
if(/wire /) print
} else if (/Start wires/) {
     flag = 1
} }' < $VERILOG_FILE |  awk -vRS=";" -vFS=" " '{print $2}' > temp3.txt

awk 'BEGIN {flag=0;}{ \
if (flag == 1){
   print;
}
} 
/Start cells/{
     flag = 1
}' < $VERILOG_FILE > temp4.txt

sed -i '/^$/d' temp3.txt
sed -i '/^$/d' temp4.txt

## Count the number of appearance of each net to decide the net cap
#eval `awk '{print "array["NR-1"]="$1}' temp3.txt` #This can be problematic (EOF issue)
array=($(awk '{print $1}' temp3.txt))
echo "Total nets: "${#array[@]}

echo "*SPEF \"IEEE 1481-1998\"" >> $SPEF_FILE
echo "*T_UNIT 1 NS" >> $SPEF_FILE
echo "*C_UNIT 1 PF" >> $SPEF_FILE
echo "*R_UNIT 1 KOHM" >> $SPEF_FILE
echo "*L_UNIT 1 UH" >> $SPEF_FILE
echo >> $SPEF_FILE
echo >> $SPEF_FILE

## this word appearance count may take some time
## should have better way
for ((i=0; i<${#array[@]}; i++))
do
    #echo -ne "*D_NET "${array[i]}" 1 " >> $SPEF_FILE
    echo -ne "*D_NET "${array[i]}" " >> $SPEF_FILE
    cnt=$(grep -o ${array[i]} temp4.txt | wc -l)
    echo "$cnt * 0.0001" | bc >> $SPEF_FILE
    echo "*END" >> $SPEF_FILE
    echo >> $SPEF_FILE
done

echo "done"

#rm -rf temp*.txt